During semiconductor manufacturing from technology development to full production it is imperative to be able to determine the limits of a particular process step as well as the extent of systematic and random defects encountered in order to minimize yield loss. It is difficult to obtain wide range of systematic and random back end of line (BEOL) or front end of line (FEOL) defectivity information as well as detailed process window information from conventional stand alone process control monitoring circuits without using up significant silicon area. Mismatch and process shift error makes conventional absolute value voltage monitoring inaccurate without specific additional reference measurements.